Tag Archives: Cypress

PSoC – Design and Implementation of a 12 Lead Portable ECG

Fully Assembled Compact, Portable 12 Lead ECG

During the academic year of 2016-2017 at McMaster University, in conjunction with Dr. DeBruin, Christina Riczu, Thomas Phan and Emilie Corcoran, we developed a compact, battery powered, 12-lead electro-cardiogram. The project won 1st place in the biomedical category at the ECE Capstone Poster Day.

The final report we handed in for the course is attached at the end of this post and includes background information, a design overview, schematics and bill of materials for the hardware we developed. This post will introduce the project and serve as a personal account of the considerations and problems associated with the portion of the project that I focused on.

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PSoC – Intro and Clock Configuration

Top an IMO derived clock not synchronized to MCLK also acting as the edge trigger. Bottom IMO derived clock synchronized to MCLK.
Top an IMO derived clock not synchronized to MCLK also acting as the edge trigger. Bottom IMO derived clock synchronized to MCLK.

I recently picked up a Cypress CY8CKIT-059 to play with for about $10 from Mouser. The kit contains a CY8C5888LTI-LP097 chip that features an ARM Cortex M3 that can run up to 80 Mhz, pretty run of the mill. However, the chip also features a small amount of CPLD resources and configurable datapaths that can be used to implement any digital logic that you can fit in. Cypress calls these blocks universal digital blocks. You can implement your own logic blocks in Verilog or use Cypress’s IP cores that are included with PSoC Creator. The idea is to avoid predefining how many UART, I2C, SPI or other interfaces to include which gives you more freedom to choose the combinations of peripherals you need rather than using pin muxes like on Microchip PIC’s and Atmel AVR’s for example. With the PSoC 5LP you can have 5 UARTs if you wanted and you can put those UARTs on any GPIO pin you want.

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